A 50nm high-k poly silicon gate stack with a buried SiGe channel

Jakschik, S.S.JakschikHoffmann, Thomas Y.Thomas Y.HoffmannCho, Hag-JuHag-JuChoVeloso, AnabelaAnabelaVelosoLoo, RogerRogerLooHyun, S.S.HyunSorada, H.H.SoradaInoue, A.A.Inouede Potter de ten Broeck, MurielMurielde Potter de ten BroeckEneman, GeertGeertEnemanSeveri, SimoneSimoneSeveriAbsil, PhilippePhilippeAbsilBiesemans, SergeSergeBiesemans2021-10-162021-10-162007https://imec-publications.be/handle/20.500.12860/12347A 50nm high-k poly silicon gate stack with a buried SiGe channelProceedings paper