Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization

Ritzenthaler, RomainRomainRitzenthalerMertens, HansHansMertensPena, VanessaVanessaPenaSantoro, GaetanoGaetanoSantoroVaisman Chasin, AdrianAdrianVaisman ChasinKenis, KarineKarineKenisDevriendt, KatiaKatiaDevriendtMannaert, GeertGeertMannaertDekkers, HaroldHaroldDekkersDangol, AnishAnishDangolLin, YongjinYongjinLinSun, ShiyuShiyuSunChen, ZheboZheboChenKim, MyungsunMyungsunKimChen, ShiChungShiChungChenMachillot, JeromeJeromeMachillotMitard, JeromeJeromeMitardYoshida, NaomiNaomiYoshidaKim, NamsungNamsungKimMocuta, DanDanMocutaHoriguchi, NaotoNaotoHoriguchi2021-10-262021-10-262018https://imec-publications.be/handle/20.500.12860/31661Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimizationProceedings paperhttps://ieeexplore.ieee.org/document/8614528