DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAM

Matagne, PhilippePhilippeMatagneNakamura, H.H.NakamuraKim, Min-SooMin-SooKimKikuchi, YoshiakiYoshiakiKikuchiHuynh Bao, TrongTrongHuynh BaoTao, ZhengZhengTaoLi, WaikinWaikinLiDevriendt, KatiaKatiaDevriendtRagnarsson, Lars-AkeLars-AkeRagnarssonBoemmels, JuergenJuergenBoemmelsMallik, ArindamArindamMallikAltamirano Sanchez, EfrainEfrainAltamirano SanchezSebaai, FaridFaridSebaaiLorant, ChristopheChristopheLorantJourdan, NicolasNicolasJourdanPorret, ClémentClémentPorretMocuta, DanDanMocutaHarada, N.N.HaradaMatsuoka, F.F.Matsuoka2021-10-252021-10-252018https://imec-publications.be/handle/20.500.12860/31309DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAMProceedings paperhttps://ieeexplore.ieee.org/document/8551632