Device and circuit level gate configuration optimization for monolayer 2D material feld-effect transistors

Verreck, DevinDevinVerreckArutchelvan, GouthamGouthamArutchelvanHeyns, MarcMarcHeynsRadu, IulianaIulianaRadu2021-10-272021-10-272019https://imec-publications.be/handle/20.500.12860/34378Device and circuit level gate configuration optimization for monolayer 2D material feld-effect transistorsProceedings paper