Wu, XuanXuanWuDens, KristofKristofDensMirabelli, GioeleGioeleMirabelliCatthoor, FranckyFranckyCatthoorReynaert, PatrickPatrickReynaert2026-06-152026-06-152025979-8-3503-5684-70271-4302https://imec-publications.be/handle/20.500.12860/59675The rapid evolution of technology and increasing demand for area-efficient RF-speed communication systems are pushing towards using the CMOS comparators to optimize speed with low power consumption. Ultra-scaled nodes hold significant potential in this context but require complex design-technology co-optimization. In this paper, we focus on the design of such a comparator with load buffer considered using IMEC’s sub-3nm calibrated PDK model. Post-layout simulation results show that the comparator operates at 32 GHz clock frequency, consuming 11.9 fJ energy per operation with 20 mVpp-diff input from a 1-V supply, for a core area of 1.44 μm2.engProceedings paper10.1109/iscas56072.2025.11043211WOS:001537918200061