Katsaragakis, ManolisManolisKatsaragakisLamprakos, ChristosChristosLamprakosKourzanov, PeterPeterKourzanovPerumkunnil, ManuManuPerumkunnilPapadopoulos, LazarosLazarosPapadopoulosCatthoor, FranckyFranckyCatthoorSoudris, DimitriosDimitriosSoudris2026-06-032026-06-032025979-8-3503-5684-70271-4302https://imec-publications.be/handle/20.500.12860/59512Recent advances in applications that are highly dependent on efficient cache utilization, in addition to the rapid growth of Edge computing systems deployed with emerging processors, generate a complex paradigm across the hardware and software continuum. In this work, we propose ARC, a novel systematic exploration methodology for application-level refinement and cache configuration mapping over emerging architectures for performance optimization. More specifically, our solution relies on workload partitioning and source code slicing mechanisms aiming to boost co-exploration of cache configuration parameters. Our proposed methodology is evaluated on a real-life IoT biomedical use case deployed over GEM5 RISC-V simulated system, showing that i) the co-impact of source code refinement and effective cache configuration leads to 61.1% execution time optimization, ii) the effective application organization and refinement leads to reduced hardware complexity. Last, we provide guidelines for application cache-friendly source code organization for performance optimization.engProceedings paper10.1109/iscas56072.2025.11044229WOS:001537918205090