0.13µm CMOS technology with optimized poly-Si / NO-oxide gate stack

Kubicek, StefanStefanKubicekJansen, PhilippePhilippeJansenBadenes, GonçalGonçalBadenesSchaekers, MarcMarcSchaekersKol'dyaev, VictorVictorKol'dyaevDeferm, LudoLudoDefermDe Meyer, KristinKristinDe MeyerKerr, DanielDanielKerrNaem, AbdallaAbdallaNaem2021-10-062021-10-061999https://imec-publications.be/handle/20.500.12860/35760.13µm CMOS technology with optimized poly-Si / NO-oxide gate stackProceedings paper