Franco, JacopoJacopoFrancoArimura, HiroakiHiroakiArimuraVici, AndreaAndreaVicide Marneffe, Jean-FrancoisJean-Francoisde MarneffeMolinaro, GiorgioGiorgioMolinaroGanguly, JishnuJishnuGangulyLukose, LeoLeoLukoseDegraeve, RobinRobinDegraeveKaczer, BenBenKaczerMertens, HansHansMertensKim, Min-SooMin-SooKimHoriguchi, NaotoNaotoHoriguchi2026-05-042026-05-0420242380-9248https://imec-publications.be/handle/20.500.12860/59279Low thermal budget RMG integration will be an enabler for future CMOS nodes. We have recently demonstrated low temperature atomic hydrogen and oxygen treatments to cure SiO2 traps and shallow HfO2 traps, respectively. Here we show that an HK post-deposition anneal is also necessary to cure deep HfO2 traps and improve SILC/TDDB reliability. We find that a conventional spike anneal at 850°C can be replaced by a 1h long anneal at reduced temperature (450-550°C). Hence, we demonstrate a new H* IL treatment with improved thermal stability to withstand the long HK PDA, and improved EOT control. The drastic NBTI improvement and effective work function increase induced by the new H* IL treatment enable the usage of a n-dipole shifter for Vth tuning in both nMOS and pMOS gate stacks. We show that Vth tuning by dipole-first insertion in NanoSheet nFETs is consistent with planar ref. data. Next, we demonstrate a low thermal budget multi-Vth gate stack scheme yielding four pMOS and four nMOS tuned Vth flavors using only two gate metals and one dipole shifter material, and adopting the same IL and HK treatments for all the device flavors to ensure sufficient reliability with minimal integration complexity.engProceedings paper10.1109/iedm50854.2024.10873365WOS:001692734400047