Process Optimization of MP18 Semi-Damascene Interconnects with Fully Self-Aligned Vias at Sub-2nm Nodes

Soussou, A.A.SoussouMarti, GiulioGiulioMartiTokei, ZsoltZsoltTokeiPark, SeonghoSeonghoParkVincent, B.B.Vincent2025-07-232024-06-062025-07-232024978-1-5106-7222-20277-786XWOS:001223585400005https://imec-publications.be/handle/20.500.12860/43998Process Optimization of MP18 Semi-Damascene Interconnects with Fully Self-Aligned Vias at Sub-2nm NodesProceedings paper10.1117/12.3010814978-1-5106-7223-9WOS:001223585400005