Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

Acharya, Lomash ChandraLomash ChandraAcharyaSharma, ArvindArvindSharmaMishra, NeerajNeerajMishraSingh, Khoirom JohnsonKhoirom JohnsonSinghDargupally, MahipalMahipalDargupallyShabarish, Nayakanti SaiNayakanti SaiShabarishMandal, AjoyAjoyMandalRamakrishnan, VenkatramanVenkatramanRamakrishnanDasgupta, SudebSudebDasguptaBulusu, AnandAnandBulusu2023-10-172023-08-112023-10-1720230278-0070WOS:001033520500018https://imec-publications.be/handle/20.500.12860/42321Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical EffortJournal article10.1109/TCAD.2022.3231173WOS:001033520500018NBTIDELAYCHALLENGES