Milojevic, DragomirDragomirMilojevicGiacomini Rocha, Leandro M.Leandro M.Giacomini RochaStephenson, J.J.StephensonStefanidis, LucasLucasStefanidisStassar, M.M.StassarNaeim, M.M.NaeimVerhelst, M.M.VerhelstBiswas, DwaipayanDwaipayanBiswasMyers, JamesJamesMyers2026-10-282026-10-282025979-8-3315-2540-81930-8833https://imec-publications.be/handle/20.500.12860/60620In this paper, we demonstrate that Multi-Plane Systolic Arrays (MP-SAs) can execute workloads in up to 2× less compute cycles than conventional Single-Plane SAs (SP-SAs), given the same compute capacity. However, increasing the number of processing planes in a 2D-IC implementation introduces interconnect overheads. Deploying MP-SAs in multi-die 3D-ICs using advanced CMOS technology reduces interconnect by up to 30%, but results in only a 5% reduction in power consumption, mostly dominated by logic. Nevertheless, for a workload that shows 30% less compute cycles, MP-SAs in 3D-ICs can achieve 17% higher energy efficiency when compared to their SP-SAs counterparts implemented as 2D-IC. Finally, despite increased power density, we demonstrate that thermal challenges can be effectively managed with appropriate cooling strategies, even in 4-Dies 3D-IC configurations.engProceedings paper10.1109/esserc66193.2025.11213951WOS:001851524100010