Veryser, BramBramVeryserStampfl, F.F.StampflGonzalez-Medina, J.M.J.M.Gonzalez-MedinaGodfrin, ClementClementGodfrinRaes, BartBartRaesWan, DannyDannyWanDe Greve, KristiaanKristiaanDe GreveLoo, RogerRogerLooShimura, YosukeYosukeShimuraPanarella, LucaLucaPanarellaWaltl, M.M.WaltlGrill, AlexanderAlexanderGrillHoussa, MichelMichelHoussaTyaginov, StanislavStanislavTyaginov2026-09-142026-09-142026979-8-3315-8972-11541-7026https://imec-publications.be/handle/20.500.12860/60350Semiconductor device reliability at cryogenic temperatures has emerged as an important research area driven by quantum computing applications. Si/SiGe heterostructures have established themselves as a leading platform for quantum devices, yet charge trapping at interfaces remains a key reliability concern. This work presents a phenomenological approach to characterize interface trapping in Si/SiGe heterostacks using fixed charge approximations. We demonstrate that threshold voltage hysteresis observed in capacitance-voltage measurements from 4.2 K to 80 K can be accurately modeled by assigning fixed charges at each channel interface. By combining this methodology with the Terman method, we extract the trap energy distribution, revealing a peak located approximately 0.1 eV below the conduction band with a maximum density of 5×1012cm−2eV−1. The extracted distributions show strong agreement with interface trap density of states reported in literature, supporting the hypothesis that fast-responding interface traps are the primary mechanism driving the observed hysteresis.engProceedings paper10.1109/irps61424.2026.11499285WOS:001844475300130ENERGY-DISTRIBUTIONTRAP DENSITY