DfT insertion and interconnect test generation for 3D stacks with JEDEC wide-IO DRAM

Deutsch, SergejSergejDeutschKeller, BrionBrionKellerChickermane, VivekVivekChickermaneGoel, Sandeep K.Sandeep K.GoelMarinissen, Erik JanErik JanMarinissen2021-10-202021-10-202012-05https://imec-publications.be/handle/20.500.12860/20599DfT insertion and interconnect test generation for 3D stacks with JEDEC wide-IO DRAMProceedings paper