Consideration of UFET architecture for the 5nm node and beyond logic transistor

Kumar Das, UttamUttamKumar DasEneman, GeertGeertEnemanVelampati, RaviRaviVelampatiChauhan, Y.Y.ChauhanJinesh, K.K.JineshBhattacharya, T.T.Bhattacharya2021-10-252021-10-2520182168-6734https://imec-publications.be/handle/20.500.12860/31092Consideration of UFET architecture for the 5nm node and beyond logic transistorJournal articlehttps://ieeexplore.ieee.org/document/8466575