ElKashlan, Rana Y.Rana Y.ElKashlanSmellie, DaanishDaanishSmellieSanchez Ramos, AlfredoAlfredoSanchez RamosKazemi Esfeh, BabakBabakKazemi EsfehRathi, AartiAartiRathiYu, HaoHaoYuYadav, SachinSachinYadavAlian, AliRezaAliRezaAlianSchreurs, DominiqueDominiqueSchreursPeralagu, UthayasankaranUthayasankaranPeralaguParvais, BertrandBertrandParvais2026-07-232026-07-232025979-8-3315-3456-12690-3938https://imec-publications.be/handle/20.500.12860/59934We present a calibrated source- and load-pull (LP) methodology for stress-aware benchmarking of GaN-on-Si (MIS/MOS) HEMTs in FR3/FR2 power amplifier applications. A 13 GHz passive LP setup, validated against on-wafer standards, achieves ±0.4 dB output power accuracy and ≤20° phase error across the Smith chart. Power budgeting guided by pulsed-IV provides realistic Psat estimates under device stress, avoiding the overestimation inherent to DC analysis. Harmonic tuning at 2f0 and 3f0 delivers ~6% efficiency enhancement, with Id–Vg monitoring confirming the absence of Vth shift or current degradation. Gate leakage is shown to impose a hard ceiling on input drive, beyond which efficiency collapses and irreversible Vth shifts occur. While demonstrated on GaN-on-Si, the methodology, linking calibration fidelity, harmonic control, and stress-aware diagnostics, generalises to other GaN variants and emerging device platforms, offering a reproducible framework for fair and reliable benchmarking under large-signal operation.engProceedings paper10.1109/apmc65046.2025.11378952WOS:001768428300303