Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation

Soussou, AssawerAssawerSoussouSchram, TomTomSchramMiyaguchi, KenichiKenichiMiyaguchiChakarov, IvanIvanChakarovParvais, BertrandBertrandParvaisErvin, JosephJosephErvin2021-10-292021-10-292020https://imec-publications.be/handle/20.500.12860/35996Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulationProceedings paperhttps://confit.atlas.jp/guide/event/ssdm2020/subject/A-5-03/advanced?cryptoId=