Cradle-to-gate Life Cycle Assessment of CMOS Logic Technologies

Boakes, LizzieLizzieBoakesGarcia Bardon, MarieMarieGarcia BardonSchellekens, V.V.SchellekensLiu, I-Y.I-Y.LiuVanhouche, B.B.VanhoucheMirabelli, G.G.MirabelliSebaai, F.F.SebaaiVan Winckel, L.L.Van WinckelGallagher, E.E.GallagherRolin, C.C.RolinRagnarsson, L. -A.L. -A.Ragnarsson2026-05-042026-05-0420232380-9248https://imec-publications.be/handle/20.500.12860/59273While concerted efforts have been made to promote greener IC manufacturing, achieving sustainable practices necessitates a comprehensive understanding of the environmental impacts associated with semiconductor fabrication. This paper presents a life cycle analysis of logic technology nodes N28 to A14 based on bottom-up modeling of a high-volume IC fabrication plant. This holistic approach provides granular results, enables sensitivity analysis, and highlights high-impact processes that could be improved to reduce environmental footprints in existing and pathfinding technologies.engCradle-to-gate Life Cycle Assessment of CMOS Logic TechnologiesProceedings paper10.1109/iedm45741.2023.10413725WOS:001693000200065