Process, circuit and system co-optimization of wafer level co-integrated FinFET with vertical nanosheet selector for STT-MRAM applications

Huynh Bao, TrongTrongHuynh BaoVeloso, AnabelaAnabelaVelosoMatagne, PhilippePhilippeMatagneRyckaert, JulienJulienRyckaertCrotti, DavideDavideCrottiYasin, FarrukhFarrukhYasinPerumkunnil, ManuManuPerumkunnilSpessot, AlessioAlessioSpessotKar, Gouri SankarGouri SankarKarMocuta, AndaAndaMocutaFurnemont, ArnaudArnaudFurnemont2021-10-272021-10-272019https://imec-publications.be/handle/20.500.12860/33189Process, circuit and system co-optimization of wafer level co-integrated FinFET with vertical nanosheet selector for STT-MRAM applicationsProceedings paperhttps://ieeexplore.ieee.org/document/8807022