Finite element analysis of an improved wafer level package using silicone under bump (SUB) layers

Gonzalez, MarioMarioGonzalezVanden Bulcke, MathieuMathieuVanden BulckeVandevelde, BartBartVandeveldeBeyne, EricEricBeyneLee, YeongYeongLeeHarkness, BrianBrianHarknessMeynen, HermanHermanMeynen2021-10-152021-10-152004https://imec-publications.be/handle/20.500.12860/8968Finite element analysis of an improved wafer level package using silicone under bump (SUB) layersProceedings paper