A 50 nm vertical Si0.70/Ge0.30/Si0.85/Ge0.15 pMOSFET with an oxide/nitride gate dielectric

Verheyen, PeterPeterVerheyenCollaert, NadineNadineCollaertCaymax, MattyMattyCaymaxLoo, RogerRogerLooVan Rossum, MarcMarcVan RossumDe Meyer, KristinKristinDe Meyer2021-10-142021-10-142001https://imec-publications.be/handle/20.500.12860/5811A 50 nm vertical Si0.70/Ge0.30/Si0.85/Ge0.15 pMOSFET with an oxide/nitride gate dielectricProceedings paper