Impact of Sub-mu m Wafer Thinning on Latch-up Risk in STCO Scaling Era

Serbulova, KaterynaKaterynaSerbulovaChen, Shih-HungShih-HungChenHellings, GeertGeertHellingsHiblot, GaspardGaspardHiblotVeloso, AnabelaAnabelaVelosoJourdain, AnneAnneJourdainDe Boeck, JoJoDe BoeckGroeseneken, GuidoGuidoGroesenekenHoriguchi, NaotoNaotoHoriguchi2023-08-102023-06-202023-07-072023-08-1020210739-5159WOS:000786179000027https://imec-publications.be/handle/20.500.12860/41855Impact of Sub-mu m Wafer Thinning on Latch-up Risk in STCO Scaling EraProceedings paper10.23919/EOS/ESD52038.2021.9574787978-1-58537-329-1WOS:000786179000027