Test and debug strategy for TSMC CoWoS stacking process-based heterogeneous 3D-IC: A silicon study

Goel, Sandeep K.Sandeep K.GoelAdham, SamanSamanAdhamWang, Min-JerMin-JerWangLee, FrankFrankLeeChickermane, VivekVivekChickermaneKeller, BrionBrionKellerValind, ThomasThomasValindMarinissen, Erik JanErik JanMarinissen2021-10-272021-10-272019-03https://imec-publications.be/handle/20.500.12860/33033Test and debug strategy for TSMC CoWoS stacking process-based heterogeneous 3D-IC: A silicon studyBook chapterhttps://doi.org/10.1002/9783527697052.ch15