Overview of bias temperature instability in scaled DRAM logic for memory transistors

O'Sullivan, BarryBarryO'SullivanRitzenthaler, RomainRomainRitzenthalerDentoni Litta, EugenioEugenioDentoni LittaSimoen, EddyEddySimoenMachkaoutsan, VladimirVladimirMachkaoutsanFazan, PierrePierreFazanJi, YunhyuckYunhyuckJiCheolygu, KimKimCheolyguSpessot, AlessioAlessioSpessotLinten, DimitriDimitriLintenHoriguchi, NaotoNaotoHoriguchi2021-10-292021-10-2920201530-4388https://imec-publications.be/handle/20.500.12860/35687Overview of bias temperature instability in scaled DRAM logic for memory transistorsJournal articlehttps://ieeexplore.ieee.org/document/9044835?source=authoralert