Kükner, HalilHalilKüknerMirabelli, GioeleGioeleMirabelliYang, ShengShengYangVerschueren, LynnLynnVerschuerenBoemmels, JuergenJuergenBoemmelsLin, Ji-YungJi-YungLinAbdi, DawitDawitAbdiFarokhnejad, AnitaAnitaFarokhnejadZografos, OdysseasOdysseasZografosHoriguchi, NaotoNaotoHoriguchiGarcia Bardon, MarieMarieGarcia BardonHellings, GeertGeertHellingsRyckaert, JulienJulienRyckaert2026-04-212026-04-2120242380-9248https://imec-publications.be/handle/20.500.12860/59135Complementary FET (CFET) device architecture with stacked n-/p-FETs is an outstanding option, promising power, performance, area scalability in the post-FinFET device era. Among several options, the double-row (DR) CFET architecture leads to reduced process complexity in the middle-of-line (MOL), and gains in logic and SRAM area, by scaling to 3.5Tracks x CPP per 2 FETs. Projections show ~40% area and ~12% power scaling potential.engProceedings paper10.1109/iedm50854.2024.10873524WOS:001692734400206