Design and synthesis of Pareto buffers offering large range runtime energy/delay trade-offs via combined buffer size and supply voltage tuning

Wang, HuaHuaWangMiranda Corbalan, MiguelMiguelMiranda CorbalanDehaene, WimWimDehaeneCatthoor, FranckyFranckyCatthoor2021-10-182021-10-1820091063-8210https://imec-publications.be/handle/20.500.12860/16520Design and synthesis of Pareto buffers offering large range runtime energy/delay trade-offs via combined buffer size and supply voltage tuningJournal article