Channel and gate stack charge trapping investigation in vertical 3D NAND devices with poly-silicon channel

Subirats, AlexandreAlexandreSubiratsArreghini, AntonioAntonioArreghiniBreuil, LaurentLaurentBreuilDegraeve, RobinRobinDegraeveVan den Bosch, GeertGeertVan den BoschLinten, DimitriDimitriLintenFurnemont, ArnaudArnaudFurnemont2021-10-242021-10-242017https://imec-publications.be/handle/20.500.12860/29520Channel and gate stack charge trapping investigation in vertical 3D NAND devices with poly-silicon channelProceedings paper