Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization

Chen, RongmeiRongmeiChenChen, LinLinChenLiang, JieJieLiangCheng, YuanqingYuanqingChengElloumi, SouhirSouhirElloumiLee, JaehyunJaehyunLeeXu, KangweiKangweiXuGeorgiev, Vihar P.Vihar P.GeorgievNi, KaiKaiNiDebacker, PeterPeterDebackerAsenov, AsenAsenAsenovTodri-Sanial, AidaAidaTodri-Sanial2023-05-042023-05-0420221063-8210WOS:000758733800001https://imec-publications.be/handle/20.500.12860/41561Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor OptimizationJournal article10.1109/TVLSI.2022.3146125WOS:000758733800001VIRTUAL-SOURCE MODELCAPACITANCEARRAYSCELLFETS