Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

Mei, BingfengBingfengMeiVernalde, SergeSergeVernaldeVerkest, DiederikDiederikVerkestDe Man, HugoHugoDe ManLauwereins, RudyRudyLauwereins2021-10-152021-10-152003https://imec-publications.be/handle/20.500.12860/7885Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo schedulingProceedings paper