3D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias

Civale, YannYannCivaleSabuncuoglu Tezcan, DenizDenizSabuncuoglu TezcanPhilipsen, HaroldHaroldPhilipsenDuval, FabriceFabriceDuvalJaenen, PatrickPatrickJaenenTravaly, YoussefYoussefTravalySoussan, PhilippePhilippeSoussanSwinnen, BartBartSwinnenBeyne, EricEricBeyne2021-10-192021-10-1920112156-3950https://imec-publications.be/handle/20.500.12860/187023D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon viasJournal article