Vertical device architecture for 5nm and beyond: device & circuit implications

Thean, AaronAaronTheanYakimets, DmitryDmitryYakimetsHuynh Bao, TrongTrongHuynh BaoSchuddinck, PieterPieterSchuddinckSakhare, SushilSushilSakhareGarcia Bardon, MarieMarieGarcia BardonSibaja-Hernandez, ArturoArturoSibaja-HernandezCiofi, IvanIvanCiofiEneman, GeertGeertEnemanVeloso, AnabelaAnabelaVelosoRyckaert, JulienJulienRyckaertRaghavan, PraveenPraveenRaghavanMercha, AbdelkarimAbdelkarimMerchaMocuta, AndaAndaMocutaTokei, ZsoltZsoltTokeiVerkest, DiederikDiederikVerkestWambacq, PietPietWambacqDe Meyer, KristinKristinDe MeyerCollaert, NadineNadineCollaert2021-10-222021-10-222015https://imec-publications.be/handle/20.500.12860/25990Vertical device architecture for 5nm and beyond: device & circuit implicationsProceedings paperhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7223689