Double patterning design split implementation and validation for the 32nm node

Drapeau, MartinMartinDrapeauWiaux, VincentVincentWiauxHendrickx, EricEricHendrickxVerhaegen, StafStafVerhaegenMachida, TakahiroTakahiroMachida2021-10-162021-10-162007https://imec-publications.be/handle/20.500.12860/12099Double patterning design split implementation and validation for the 32nm nodeProceedings paperwww.spie.org