Modelling and mitigation of time-zero variability in sub-16nm FinFET-based STT-MRAM memories

Hartmann, MatthiasMatthiasHartmannKukner, HalilHalilKuknerAgrawal, PrashantPrashantAgrawalRaghavan, PraveenPraveenRaghavanVan der Perre, LiesbetLiesbetVan der PerreDehaene, WimWimDehaene2021-10-222021-10-222014https://imec-publications.be/handle/20.500.12860/23907Modelling and mitigation of time-zero variability in sub-16nm FinFET-based STT-MRAM memoriesProceedings paperhttp://dl.acm.org/citation.cfm?id=2591573