Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)

Sisto, GiulianoGiulianoSistoChen, RongmeiRongmeiChenChou, RichardRichardChouVan der Plas, GeertGeertVan der PlasBeyne, EricEricBeyneRod MetcalfeMilojevic, DragomirDragomirMilojevic2022-07-052022-03-262022-07-042022-07-052021-11-041544-5623WOS:000766322000004https://imec-publications.be/handle/20.500.12860/39525Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)Proceedings paper10.1109/SLIP52707.2021.00011978-1-6654-0083-1WOS:0007663220000043D EDA flow