Impact of p-well implantation parameters compatible with deep submicron CMOS techology on junction leakage

Poyai, AmpornAmpornPoyaiRittaporn, IttiIttiRittapornRooyackers, RitaRitaRooyackersSimoen, EddyEddySimoenClaeys, CorCorClaeys2021-10-152021-10-152003https://imec-publications.be/handle/20.500.12860/8035Impact of p-well implantation parameters compatible with deep submicron CMOS techology on junction leakageProceedings paper