Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

Chen, RongmeiRongmeiChenSisto, GiulianoGiulianoSistoJourdain, AnneAnneJourdainHiblot, GaspardGaspardHiblotStucchi, MicheleMicheleStucchiKakarla, NaveenNaveenKakarlaChehab, BilalBilalChehabSalahuddin, Shairfe MuhammadShairfe MuhammadSalahuddinSchleicher, FilipFilipSchleicherVeloso, AnabelaAnabelaVelosoHellings, GeertGeertHellingsWeckx, PieterPieterWeckxMilojevic, DragomirDragomirMilojevicVan der Plas, GeertGeertVan der PlasRyckaert, JulienJulienRyckaertBeyne, EricEricBeyne2022-08-252022-07-092022-08-2520212380-9248WOS:000812325400034https://imec-publications.be/handle/20.500.12860/40084Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm nodeProceedings paper10.1109/IEDM19574.2021.9720528978-1-6654-2572-8WOS:000812325400034