Scalable gate-level models for power and timing analysis

Badaroglu, MustafaMustafaBadarogluVan der Plas, GeertGeertVan der PlasWambacq, PietPietWambacqDonnay, StephaneStephaneDonnayGielen, GeorgesGeorgesGielenDe Man, HugoHugoDe Man2021-10-162021-10-162007-05https://imec-publications.be/handle/20.500.12860/11668Scalable gate-level models for power and timing analysisProceedings paper