Moeneclaey, BartBartMoeneclaeyLambrecht, JorisJorisLambrechtParisi, AngeloAngeloParisiVan Kerrebrouck, JorisJorisVan KerrebrouckCoudyzer, GertjanGertjanCoudyzerKankuppe Raghavendra Swamy, Anirudh PraveenAnirudh PraveenKankuppe Raghavendra SwamyYin, XinXinYinMartens, EwoutEwoutMartensCraninckx, JanJanCraninckxOssieur, PeterPeterOssieur2026-04-152026-04-1520260018-9200https://imec-publications.be/handle/20.500.12860/59096We present a 7-bit wireline digital-to-analog converter (DAC), fabricated in 5-nm FinFET CMOS. The number of source-series terminated (SST) cells in the output stage is reduced to 34 by employing cells with relative weight 1 and 4. Each differential cell integrates two single-ended three-stage 8:1 return-to-zero (RZ) multiplexers with an integrated SST driver and a clock pulse generator (CPG), which generates the required clock pulses for the multiplexers from an eight-phase clocking scheme. The clock buffers driving these cells feature shunt inductors to reduce power consumption and jitter. At 150 GSa/s, the effective number of bits (ENOB) was measured to be 4.1 b for a 72.8-GHz sinewave. The DAC consumes 621 mW from a 0.9- and 0.96-V supply. Eye diagrams of 150-GBd NRZ, PAM-4, and PAM-6 are demonstrated, pre-equalized using a 10-tap feedforward equalizer.engJournal article10.1109/jssc.2026.3654029WOS:001669334900001