Joint-optimization for SRAM and Logic for 28nm node and below

Verhaegen, StafStafVerhaegenSmayling, Michael C.Michael C.SmaylingDe Bisschop, PeterPeterDe BisschopLaenens, BartBartLaenens2021-10-182021-10-182010https://imec-publications.be/handle/20.500.12860/18273Joint-optimization for SRAM and Logic for 28nm node and belowProceedings paper