CDM ESD testing of a 3D TSV stacked IC chip

Nagata, NagataNagataNagataTakaya, SatoshiSatoshiTakayaIkeda, HiroakiHiroakiIkedaLinten, DimitriDimitriLintenScholz, MirkoMirkoScholzChen, Shih-HungShih-HungChenHasegawa, KeiichiKeiichiHasegawaShintani, TaizoTaizoShintaniSawada, MasanoriMasanoriSawada2021-10-222021-10-222014-10https://imec-publications.be/handle/20.500.12860/24308CDM ESD testing of a 3D TSV stacked IC chipMeeting abstract