An analytical model of MOS admittance for border trap density extraction in high-k dielectrics of III-V MOS devices

Vais, AbhitoshAbhitoshVaisMartens, KoenKoenMartensLin, DennisDennisLinMocuta, AndaAndaMocutaCollaert, NadineNadineCollaertThean, AaronAaronTheanDe Meyer, KristinKristinDe Meyer2021-10-232021-10-2320160018-9383https://imec-publications.be/handle/20.500.12860/27425An analytical model of MOS admittance for border trap density extraction in high-k dielectrics of III-V MOS devicesJournal articlehttp://ieeexplore.ieee.org/document/7731244/