Logic via printability enhancement using restricted via placement and exhaustive SRAF placement on a staggered grid

Woltgens, PieterPieterWoltgensColina, AlbertoAlbertoColinaRio, DavidDavidRioDelorme, MaxMaxDelormeKovalevich, TatianaTatianaKovalevichThiam, ArameArameThiamVan Roey, FriedaFriedaVan RoeyZografos, OdysseasOdysseasZografos2022-12-192022-09-192022-09-262022-12-192022-05-26978-1-5106-4977-40277-786XWOS:000850450900016https://imec-publications.be/handle/20.500.12860/40464Logic via printability enhancement using restricted via placement and exhaustive SRAF placement on a staggered gridProceedings paper10.1117/12.2614260978-1-5106-4978-1WOS:000850450900016Electrical & electronic engineering