Low energy clustered instruction fetch and split loop cache architecture for long instruction word processors

Jayapala, MuraliMuraliJayapalaBarat, F.F.BaratOp de beeck, PieterPieterOp de beeckCatthoor, FranckyFranckyCatthoorDe Coninck, G.G.De Coninck2021-10-142021-10-142001https://imec-publications.be/handle/20.500.12860/5371Low energy clustered instruction fetch and split loop cache architecture for long instruction word processorsProceedings paper