Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

Badaroglu, MustafaMustafaBadarogluTiri, KrisKrisTiriDonnay, StephaneStephaneDonnayWambacq, PietPietWambacqVerbauwhede, IngridIngridVerbauwhedeGielen, GeorgesGeorgesGielenDe Man, HugoHugoDe Man2021-10-142021-10-142002https://imec-publications.be/handle/20.500.12860/5976Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transientsProceedings paper