A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology

Chen, Wen-ChiehWen-ChiehChenChen, Shih-HungShih-HungChenHuang, Man-ChingMan-ChingHuangChang, Shu-WeiShu-WeiChangHellings, GeertGeertHellingsGroeseneken, GuidoGuidoGroeseneken2025-04-302024-08-052025-04-3020250018-9200WOS:001279004700001https://imec-publications.be/handle/20.500.12860/44270A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS TechnologyJournal article10.1109/JSSC.2024.3424264WOS:001279004700001VOLTAGE I/O BUFFERCMOSDRIVER