Test-architecture optimization for TSV-based 3D stacked ICs

Noia, BrandonBrandonNoiaGoel, Sandeep KumarSandeep KumarGoelChakrabarty, KrishnenduKrishnenduChakrabartyMarinissen, Erik JanErik JanMarinissenVerbree, JoukeJoukeVerbree2021-10-182021-10-182010https://imec-publications.be/handle/20.500.12860/17707Test-architecture optimization for TSV-based 3D stacked ICsProceedings paperhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5512787