Beyne, SofieSofieBeyneKubicek, StefanStefanKubicekGodfrin, ClementClementGodfrinRaes, BartBartRaesVan Caekenberghe, T.T.Van CaekenbergheDe Backer, JohanJohanDe BackerHermans, YannickYannickHermansTreska, FergoFergoTreskaKaushik, ShuchiShuchiKaushikJiang, Y.Y.JiangChou, BiancaBiancaChouSarkar, TarunTarunSarkarLi, Y.Y.LiSharma, Y.Y.SharmaBaudot, SylvainSylvainBaudotPinotti, L.L.PinottiShimura, YosukeYosukeShimuraLoo, RogerRogerLooKenens, BartBartKenensVande Weeghde, J.J.Vande WeeghdeVrancken, EviEviVranckenVandersmissen, KevinKevinVandersmissenMitard, JeromeJeromeMitardDevriendt, KatiaKatiaDevriendtWan, DannyDannyWanDe Greve, KristiaanKristiaanDe Greve2026-08-212026-08-212025979-8-3315-6786-62380-9248https://imec-publications.be/handle/20.500.12860/60089We demonstrate a 300mm process for 2 types of SiMOS quantum dot spin qubit device architectures enabled by EUV lithography. First, we show an overlapping gates process for spin qubits, where the gates are fabricated for the first time using 0.33NA EUV lithography. We report excellent reproducibility, full wafer room temperature functionality and good quantum dot and qubit metrics at 10mK. Second, to enable qubit scalability, we demonstrate a single-layer gate device architecture fabricated with 0.33NA EUV patterning of the gate, and 2 damascene EUV BEOL layers.engProceedings paper10.1109/iedm50572.2025.11353541WOS:001701480300043