Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

Zhou, LongdaLongdaZhouLiu, QianqianQianqianLiuYang, HongHongYangJi, ZhigangZhigangJiXu, HaoHaoXuWang, GuileiGuileiWangSimoen, EddyEddySimoenJiang, HaojieHaojieJiangLuo, YingYingLuoKong, ZhenzhenZhenzhenKongBai, GuobinGuobinBaiLuo, JunJunLuoYin, HuaxiangHuaxiangYinZhao, ChaoChaoZhaoWang, WenwuWenwuWang2022-07-072021-11-022022-07-0720212168-6734WOS:000622098400034https://imec-publications.be/handle/20.500.12860/38115Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process OptimizationJournal article10.1109/JEDS.2021.3057662WOS:000622098400034