Balasubramanian, ShankkarShankkarBalasubramanianVaesen, KristofKristofVaesenWambacq, PietPietWambacqWulff, CarstenCarstenWulff2026-07-162026-07-1620252573-9603https://imec-publications.be/handle/20.500.12860/59899This letter presents a frequency quadrupler with 32% fractional bandwidth (66–92 GHz) and 5% peak power-added efficiency (PAE), capable of operating with an input power of 0 dBm. The quadrupler consisting of two cascaded frequency doublers uses a multiport driven push-push complementary architecture for the first stage to generate differential signals for the second doubler with high fundamental harmonic rejection. The second doubler based on the nMOS-based push-push architecture uses gain enhancement to achieve a maximum conversion gain of –4 dB for the quadrupler. The quadrupler with an output saturation power (P sat ) of –2.6 dBm achieves first- to third-harmonic rejections of more than 36 dBc across the 3-dB bandwidth. The compact quadrupler has a core area of 0.09 mm2, while consuming a DC power of 6.2 mW from a 0.8 V supply with an input power of 0 dBm at 20 GHz.engJournal article10.1109/lssc.2025.3614381WOS:0015898330000012573-9603