Modelling negative bias temperature instabilities in hole-channel metal-oxide-semiconductor field effect transistors with ultrathin gate oxide layers

Houssa, MichelMichelHoussaAoulaiche, MarcMarcAoulaicheAutran, L.L.AutranParthasarathy, C.C.ParthasarathyRevil, N.N.RevilVincent, E.E.Vincent2021-10-152021-10-152004https://imec-publications.be/handle/20.500.12860/9058Modelling negative bias temperature instabilities in hole-channel metal-oxide-semiconductor field effect transistors with ultrathin gate oxide layersJournal article