Investigation of high-k-metal gate integration for sub 45 nm planar bulk CMOS technologies

Singanamalla, RaghunathRaghunathSinganamalla2021-10-172021-10-172008-12https://imec-publications.be/handle/20.500.12860/14483Investigation of high-k-metal gate integration for sub 45 nm planar bulk CMOS technologiesPHD thesis